The present invention relates to a semiconductor device having a trench-type buried insulating gate, and more specifically, to a semiconductor device improved in trench density (the number of trenches per unit area) by improving a trench arrangement pattern and a manner of source/base simultaneous contact.
In a conventional semiconductor device serving as a switching element, a trench structure is known to be more widely employed. In the semiconductor device having a trench structure, the number of cells per unit chip area can be increased as compared to the semiconductor device having the planar structure, with the result that "on"-resistance is successfully reduced.
FIG. 1 is a plan view of a structure of a semiconductor layer of a semiconductor device having the trench structure of this type. FIG. 2 is a cross-sectional view of the semiconductor layer taken along the II--II line of FIG. 1. FIG. 2 further shows an electrode structure (omitted in FIG. 1) in addition to the sectional structure of the semiconductor layer.
In the semiconductor device, a p-type base layer 2 is formed on an n.sup.- -type substrate 1. In the surface of the p-type base layer 2, an n.sup.+ -type source layer 3 of 2.6 .mu.m width is selectively formed in stripes so as to expose the p-type base layer 2 of 1 .mu.m between adjacent n.sup.+ -type source layer stripes 3.
A trench 4 of 0.6 .mu.m width is formed along a center line of the n.sup.+ -type source layer 3. The trench 4, in the depth direction, passes through the p-type base layer and extends to the n.sup.- -type substrate 1. Consequently, the interval T.sub.0 between adjacent trenches 4 results in 3 .mu.m. Furthermore, a gate electrode 6 formed of polysilicon etc. is buried in each of the trenches with a gate insulating film 5 interposed therebetween.
An interlayer insulating film 7 is formed over each of the trenches 4 including a center region of each of the n.sup.+ -type source layers 3 at both sides to the trench 4. The interlayer insulating film 7 are thus arranged in stripes. A source electrode 8 is formed so as to be in contact with the n.sup.+ type source layer 3 and the p-type base layer 2, which are exposed between the interlayer insulating film stripes 7.
The contact region, in which the n.sup.+ -type source layer 3 is in contact with the p-type base layer 2, is formed between adjacent trenches. Since a sufficient alignment margin (1 .mu.m) is set, a short circuit between the contact region and the trench gate can be prevented.
On the other hand, a drain electrode 10 is formed on a rear surface of the n.sup.- type substrate 1 with an n.sup.+ type drain layer 9 sandwiched therebetween. The semiconductor device formed herein is a vertical MOSFET due to the n.sup.+ type drain layer. In the case where a semiconductor device has a p.sup.+ type drain layer in place of the n.sup.+ type drain layer 9, the semiconductor device is referred to a vertical IGBT. On the other hand, if a semiconductor has a p.sup.+ type drain layer and the width and depth of the trench 4, the interval between the adjacent trenches 4 and the number of the source and base contacts to that of the trenches are appropriately set so as to accumulate holes in the n.sup.- type substrate 1, the semiconductor device is referred to an IEGT.
In view of reducing the "on" resistance, the channel width per unit area has been tried to be elongated, thereby improving the channel density (the number of channels per unit area). As known well, since the channel is formed in an "on"-state within the p-type base layer 2 along the side wall of the trench 4, the channel density is increased in proportion to the trench density. Therefore, to improve the channel density, it is effective to improve the trench density. The trench density can be increased by, for example, narrowing the interval T.sub.0 between trenches.
However, in the aforementioned semiconductor device, it is required to set the alignment margin between the contact region and the trench gate. Since the control of the interval T.sub.0 between the trenches is restricted by the alignment margin, it is difficult to narrow the trench interval T.sub.0. For this reason, it is not easy to improve the trench density.